Multi-ported register files are becoming increasingly prevalent in computing system designs. Multi-ported register files are particularly desirable for high performance computing, which may be implemented within a mobile application, like a cellular telephone, a personal digital assistant (PDA), etc., and/or as may be implemented in stationary applications, such as a mainframe computer, a personal computer (PC), etc. In general, memory systems conventionally have static random access memories (SRAMs), with single read and write ports, whereby a resource can perform either a write or a read at one time (i.e., the resource cannot perform both a read and write at the same time). Many integrated circuit (IC) based register files are implemented using such SRAMs having multiple ports. Such multi-ported SRAMs may have dedicated read and write ports, thus enabling read and write operations to be performed simultaneously via the respective ports.
It is often desirable to have a system where multiple agents (or applications) can access the same memory for performing reads and writes in parallel. As an example, such parallelism is often desirable in graphic processing to enable computations (e.g., pertaining to shades and colors, etc.) to be performed quickly so the user does not perceive a flicker or slowness in graphic transitions, but instead perceives a smooth transition of graphics. To achieve such efficient graphics computations, it becomes desirable to have a central memory with multiple agents being able to access the same, central memory. Accessing the same memory by multiple agents is often desirable because it reduces coherency issues. That is, by accessing the same memory, the multiple agents are assured to be accessing the latest data at that point in time without running into coherency issues, as are often encountered in many hierarchical cache systems.
Multi-ported memories are quite prevalent in current microprocessor architectures because they are used quite often as level zero (or “L0”) cache. Conventional multi-ported memories in microprocessors operate based on sequence clocks. In particular, the system may have a clock generator based on phase lock loop (PLL), which generates a very high frequency, very accurate clock signal. The clock signal is supplied to the multi-ported memory, which uses the clock signal as a reference for synchronizing its operations. The clock signal has a periodically repeating high phase and low phase. In conventional multi-ported memories, a memory access operation (e.g., a read or write) may be performed in one phase (e.g., in the high phase) of the clock signal, and in the other phase (e.g., in the low phase) an operation is not performed. Thus, in conventional multi-ported memories, one memory access operation (e.g., a read or write) may be performed on each port per clock cycle.
Accordingly, register files are normally operated based on reference to a synchronization clock. A high-precision clock signal generator is thus required to ensure the proper synchronization of operations by the register files. Because the synchronization is dependent on the reference clock signal, such an implementation is undesirably prone to clock duty cycle, skew, and/or jitter issues. Additionally, because the conventional multi-ported register file implementation operates with reference to a clock signal running at high frequencies, power consumption tends to be very high in such an implementation.